1. Field of the Invention
The present invention generally relates to fabrication of Dynamic Random Access Memory (DRAM) cells and, more particularly, to increasing capacitor storage for DRAM cells.
2. Background Description
Increased capacitor charge storage is critical in future DRAM cells. One way to achieve this objective is to increase the area of the storage node. This must be accomplished without increasing the overall cell dimension for a given dielectric thickness. Many suggestions have been proposed in the literature to increase the capacitor area in DRAM cells such as a corrugated capacitor structure, a three dimensional capacitor structure, a pillar in trench structure, a rough polysilicon structure, and a ring structure. Some of the drawbacks of these proposals are that complex multi-processing steps increase processing costs of the microelectronic device and decrease device yield and that it is very difficult to control the structure and multi-layer film at nanometer dimensions. Diffusion controls film roughness. As a result, the process will not be able to extend in the nanometer scale dimension.
In the past, damascene metal interconnect and planarization processes had been developed and used for Back End of the Line (BEOL) metal wiring for microelectronic devices (IBM Journal of Research and Developments, Vol. 39, No. 1, January 1995, pp. 167-188 and IBM Journal of Research and Developments, Vol. 39, No. 2, March 1995, pp. 215-227).